Blocker and Jitter-Tolerant Continuous-Time Sigma-Delta ADCs
Continuous-time (CT) Sigma-Delta ADCs are a promising candidate for high-speed receiver applications, such as software-defined radio (SDR), due to its inherent anti-aliasing and signal filtering, potential lower power consumption because of less stringent requirements on Op-Amps, and easy reconfigurability.
Contrast to applications such as data acquisition and sensor readout, the performance of ADCs in receiver applications is defined by not only the desired in-band (IB) signals, but also the out-of-band (OoB) blockers which are also processed. Consequently, OoB blockers, which could be orders of magnitudes larger than the desired in-band signals, are usually the performance-defining signal component in receiver applications, which could lead to overload of the modulator, causing strong signal distortion or even a complete loss of the system functionality, or reciprocal mixing, i.e. the jitter-induced noise due to OoB blockers degrading the maximally achievable SNR of the in-band signals. An ADC with blocker rejection can reduce its own specifications, and result in a more efficient realization ().
Furthermore, clock jitter heavily influences the performance of CT Sigma Delta modulators, and this effect becomes more severe as a higher modulator bandwidth often requires a faster clock. In order to achieve the same SNR for the modulator, smaller jitter is required for the higher clock rate, leading to larger power consumptions in the clock synthesis and distribution, which is comparable to the power consumption of the modulator itself.
The goal of this project is to investigate and implement blocker and jitter-tolerant CT Sigma-Delta ADCs that are suitable for modern multi-standard wireless communications. Such an ADC should aim not only at achieving the best figure-of-merit (FoM), but also at helping to reduce the design specifications of other components in the entire receiver architecture in order to achieve a better overall power-efficiency.
 R. Ritter and M. Ortmanns
Continuous-Time Delta-Sigma ADCs With Improved Interferer Rejection
IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 5, no. 4, pp. 500–513, Dec. 2015.