High resolution SAR ADC employing Sigma Delta DACs
ADCs are essential building blocks for almost all electronic systems, they represent the key element that allows the digital representation of any electrical signal located in the analog domain, and hence these by-nature analog signals could be processed by the latest sophisticated digital processing units only after well A/D conversion in the ADCs.
With increasing interest of a very highly accurate representation of signals in environmental and medical applications, high resolution ADCs gain increased importance. In a world full of sensors an attractive application for high resolution ADC is the read-out circuitry for a sensor array, there, a high accuracy ADC is to be multiplexed and shared between many sensors.
SAR ADCs are becoming very popular in the recent years because they make use of the improved digital capabilities to implement a Nyquist-rate ADC. The conventional SAR ADC concept relies on a binary weighted capacitor array to perform D/A conversion in a digitally-controlled loop. This architecture has dominated the state of the art designs with the best power efficiency among all Nyquist-rate ADCs. However, this architecture was limited in resolution due to reliance on high element matching. Therefore, the effective A/D resolution of SAR ADCs was most of the time limited below 13 bit.
The available state of the art solutions to build high resolution ADCs include firstly the oversampling and noise shaping ADCs, which are very good candidates for that except the fact that they lack the multiplexing capabilities since they perform signal averaging and no sample-to-sample conversion, like their Nyquist-rate counterparts. The main architecture that is currently available to achieve high resolution and at same time Nyquist-rate conversion is the pipeline ADC, however, due to the need of residual amplifier(s) the power consumption of these ADCs usually exceeds their SAR counterparts by several order of magnitudes. Finally, the incremental ADCs achieve a very high signal to noise ratio at low power consumption and based on sample-to-sample conversion. However, they present very low conversion rates and are mainly developed to deal with static/DC inputs which prevents multiplexing.
The project main objective is to make use of the efficient SAR ADC architecture and get over its resolution limitation due to the conventional capacitor DAC structure. Therefore, the project aims to introduce another DAC structure that makes use of a sigma-delta DAC in the feedback path of the SAR. The SD-DAC is capable of achieving high resolution conversion without reliance on element matching but on noise shaping and filtering.