Freely running Σ∆ ADCs have been extensively studied concerning their stability using heuristics, transient simulations or analytical equations. However, the stability of I-Σ∆ modulators have not been particularly studied due to their similarity with their freely running counterparts. However, these analyses should be handled with caution since the resetting action after every OSR cycle introduces a major difference in the stability behavior. As an example, the resetting action of I-Σ∆ modulators can prevent the occurrence of limit cycles as they frequently occur especially in single bit freely running modulators. While – mostly heuristic – criteria exist to determine the stability of Σ∆ ADCs such as the famous Lee criterion, they are typically not very accurate – especially for single bit modulators – since they mostly assume a linear model for internal quantizer.
Only recently, another possibility to predict the stability of a Σ∆ ADC has been presented in the State of the Art, where the nonlinear modulator is modeled as a mixed-logical dynamical (MLD) system to investigate the modulator stability. MLD systems have been introduced for the modeling of nonlinear systems to allow for the treatment of both the linear and the nonlinear part of the system in one joint optimal control problem (OCP). The MLD system model is used to compute the worst-case input signal, i.e. the input signal which drives the modu-lator maximally unstable, by solving the resulting OCP using a mixed integer linear program (MILP) for a finite number of cycles.
In this work this State-of-the-Art MLD system shall be implemented and further improved leading to a deeper understanding of the stability of incremental Delta Sigma Converters.
What we expect:
- Good understanding of ADCs and Control Theory
- Experience in Matlab and Simulink
- Organized and well documented research and dedication to successful work