The trend towards Artificial Intelligence (AI) has gathered significant impact and demands new hardware solutions. The distinct program structure of neural networks, requires highly parallelized and data-intensive operations to be executed which is facilitated by dedicated inference processors.
A promising approach for building such processors is mixed-signal hardware. Such circuits conduct the most commonly used multiply-accumulate (MAC) operation using analog quantities (charge, voltage, …). In-memory-compute (IMC) systems are an example for such circuits. They elegantly merge the needs of the inference hardware for memory and a smart data-flow with analog compute circuits.
The goal of this thesis is to reimplement an existing In-Memory-Compute Design (planar, 28nm) within a 16nm FinFET technology. Therefore, the reusability of existing design resources has to be evaluated and proper adaptions has to be made regarding FinFET peculiarities. Furthermore, a design layout should be developed including the assessment of layout-related parasitic influences. The architecture to work on comprises standard SRAM enhanced by Switched-Capacitor circuitry (various CDACs) and a SAR ADC.
What we expect:
- Good understanding of Switched-Capacitor circuits and passive CDAC architectures (e.g. Integrated Analog Circuits, Integrated Interface Circuits)
- Ideally some knowledge of Cadence Virtuoso (e.g. Project Analog CMOS Circuit Design)
- Organized and well documented research and dedication to successful work
What we provide:
- Experience in the field of digital, analog and mixed-signal design using industry-standard tools and leading-edge simulation concepts
- All tools provided and made easily available, also for remote-work
- An insight into state-of-the-art design techniques for ASICs