Contact
Room: 43.2.409
Tel.: +49 (0)731 - 50 26225
ahmed.abdelaal(at)uni-ulm.de
M.Sc. Ahmed Abdelaal
Ahmed Abdelaal received the B.Sc degree in Electronics Engineering from the German University in Cairo (GUC), Egypt, 2016. Afterwards, he received the M.Sc degree in 2018 from Ulm University, Germany, where he is currently working towards his PhD under the supervision of Professor Dr.-Ing. Maurits Ortmanns. His research interest is high-speed continuous-time sigma-delta modulators.
Student theses
[mt] = Master thesis, [rp] = Bachelor thesis
Past theses
- Santiago Noriega-Alvarez
Negative-Resistance Assisted Amplifier [mt] - Fouad Elbadry
Automated Opamp design using Cadence-Virtuoso Optimization Tool [rp] - Omar Ismail
Dual quantization CT-Sigma-Delta ADC for wide-band applications [mt]
Publications
2025
16.
D. -. Wiens,
A. Abdelaal,
B. Driemeyer,
J. Becker,
J. G. Kauffman and
M. Ortmanns,
"A Digitizing Integrator–Differentiator TIA With 1-MHz Bandwidth and 93-pArms Sensitivity in 28-nm CMOS",
IEEE Journal of Solid-State Circuits ( Early Access ),
Nov.
2025.
| DOI: | 10.1109/JSSC.2025.3626825 |
15.
M. Dalla Longa,
F. Conzatti,
O. Ismail,
A. Abdelaal,
J. G. Kauffman and
M. Ortmanns,
"A 470-μW, 102.6-dB DR, 20-kHz BW Calibration-Free ΔΣ Modulator With SFDR in Excess of 110 dBc Using an Intrinsically Linear 13-Level DAC",
IEEE Journal of Solid-State Circuits, Volume: 60, Issue: 11, Page(s): 4059 - 4072,
Nov.
2025.
| DOI: | 10.1109/JSSC.2025.3553310 |
14.
J. Conrad,
S. Wilhelmstätter,
H. Mandry,
P. Kässer,
A. Abdelaal,
R. Asthana,
V. Belagiannis and
M. Ortmanns,
"PSumSim: A Simulator for Partial-Sum Quantization in Analog Matrix-Vector Multipliers",
IEEE International Symposium on Circuits and Systems (ISCAS), London, United Kingdom, pp. 1-5,
May
2025.
| DOI: | 10.1109/ISCAS56072.2025.11043442 |
13.
A. Abdelaal,
J. G. Kauffman,
J. Becker,
M. Dalla Longa,
F. Conzatti and
M. Ortmanns,
"A Calibration-free 80MHz CT DSM Using Dual Quantization and ISI Shuffler Achieving 106.2dB SFDR",
IEEE Custom Integrated Circuits Conference (CICC), Boston, MA, USA,
Apr.
2025.
| DOI: | 10.1109/CICC63670.2025.10982928 |
12.
D. -. Wiens,
A. Abdelaal,
B. Driemeyer,
J. Becker,
J. G. Kauffman and
M. Ortmanns,
"A Direct Digitizing, 1MHz Bandwidth, 28fA/√Hz Current Sensing Front-End Based on a Mixed-Signal Integrator-Differentiator TIA in 28nm CMOS",
IEEE Custom Integrated Circuits Conference (CICC), Boston, MA, USA,
Apr.
2025.
| DOI: | 10.1109/CICC63670.2025.10983397 |
2024
11.
A. Abdelaal,
M. Pietzko,
J. G. Kauffman,
A. Jain and
M. Ortmanns,
"ΔΣ Modulators Employing MASH DSM DAC-Based Dual Quantization",
IEEE Transactions on Circuits and Systems I: Regular Papers ( Volume: 72, Issue: 1, Page(s) 71-84, January 2025),
Aug.
2024.
| DOI: | 10.1109/TCSI.2024.3448224 |
10.
A. Abdelaal,
M. Pietzko,
J. Ungethüm,
J. G. Kauffman and
M. Ortmanns,
"Using Negative-R Assisted Integrators in Wide-band Delta-Sigma Modulators",
IEEE International Symposium on Circuits and Systems (ISCAS), Singapore,
Jul.
2024.
| DOI: | 10.1109/ISCAS58744.2024.10558442 |
9.
M. Pietzko,
J. Ungethüm,
A. Abdelaal,
J. G. Kauffman and
M. Ortmanns,
"A 600MS/s 10-bit SAR ADC with unit via-based delta-length C-DAC in 22nm FDSOI",
IEEE International Symposium on Circuits and Systems (ISCAS), Singapore,
May
2024.
| DOI: | 10.1109/ISCAS58744.2024.10558087 |
2023
8.
J. Ungethüm,
M. Pietzko,
A. Abdelaal,
J. G. Kauffman and
M. Ortmanns,
"A Chopped 6-bit 1.6 GS/s SAR ADC Utilizing Slow Decision Information in 22 nm FDSOI",
ESSCIRC 2023- IEEE 49th European Solid State Circuits Conference (ESSCIRC),
Sep.
2023.
| DOI: | 10.1109/ESSCIRC59616.2023.10268704 |
2022
7.
M. A. Mokhtar,
A. Abdelaal,
M. Sporer,
J. Becker,
J. G. Kauffman and
M. Ortmanns,
"A 0.9-V DAC-Calibration-Free Continuous-Time Incremental Delta-Sigma Modulator Achieving 97-dB SFDR at 2 MS/s in 28-nm CMOS",
IEEE Journal of Solid-State Circuits, Volume: 57, Issue: 11,
Nov.
2022.
| DOI: | 10.1109/JSSC.2022.3160325 |
2021
6.
A. Abdelaal,
M. Pietzko,
M. A. Mokhtar,
J. G. Kauffman and
M. Ortmanns,
"FIR filter with Symmetric Non-Equal Coefficients for CT Delta-Sigma Modulators",
IEEE International Symposium on Circuits and Systems (ISCAS), Daegu, Korea (Online),
May
2021.
5.
M. Pietzko,
J. Wagner,
A. Abdelaal,
J. G. Kauffman and
M. Ortmanns,
"Influence of Excess Loop Delay on the STF of Continuous-Time Delta-Sigma Modulators",
IEEE International Symposium on Circuits and Systems (ISCAS), Daegu, Korea (Online),
May
2021.
4.
M. A. Mokhtar,
A. Abdelaal,
M. Sporer,
J. Becker,
J. G. Kauffman and
M. Ortmanns,
"A 0.9-V Calibration-Free 97dB-SFDR 2-MS/s ContinuousTime Incremental Delta-Sigma ADC Utilizing Variable Bit-Width Quantizer in 28nm CMOS",
IEEE Custom Integrated Circuits Conference (CICC), Texas, USA (Virtual),
Apr.
2021.
2020
3.
A. Abdelaal,
J. G. Kauffman,
M. A. Mokhtar and
M. Ortmanns,
"A Comparative Study of ISI Errors in Different DAC Structures for CT Delta-Sigma Modulators",
IEEE International Symposium on Circuits and Systems (ISCAS), Sevilla, Spain,
Oct.
2020.
2.
M. A. Mokhtar,
P. Vogelmann,
A. Abdelaal,
J. G. Kauffman and
M. Ortmanns,
"FIR DACs in CT Incremental Delta-Sigma Modulators",
IEEE International Symposium on Circuits and Systems (ISCAS), Sevilla, Spain,
Oct.
2020.
2019
1.
A. Jain,
A. Abdelaal and
M. Ortmanns,
"Effective Filtering of Requantization Error in Dual Quantized CTDSM using FIR DAC",
IEEE International Symposium on Circuits and Systems (ISCAS), Sapporo, Japan, pp. 1-5.,
May
2019.
Research Assistent
