Wide-band Continuous-time Delta-Sigma Analog to Digital converter Design
Continuous-Time Delta-Sigma Modulators (CTDSMs) have recently become essential in both wireless and wired broadband communications. Their inherent anti-aliasing capabilities and ability to meet relaxed sampling requirements make them preferable to their discrete-time counterparts.
This project focuses on the design, development, and testing of Delta-Sigma Modulators for wide-band applications. A key challenge in high-speed operation is the limitation of the oversampling ratio, necessitating the use of multi-bit quantizers to achieve a high signal-to-noise ratio (SNR). However, multi-bit digital-to-analog converters (DACs) introduce non-linearity, leading to distortion and degradation in and the signal-to-noise-and-distortion ratio (SNDR). For this reason, it is usually necessary to calibrate the multi-bit DAC with significant effort. By using dual quantization with a digital delta-sigma modulator (DDSM), high linearity can also be achieved without any calibration.
Another key challenge is the design of operational amplifiers (opamps) used in the RC integrators, which must achieve a sufficient gain-bandwidth product (GBW), often reaching the GHz range, while maintaining good linearity. This typically results in high power consumption. An alternative approach involves the use of GM-C integrators, which offer improved power efficiency but suffer from non-linearity.
Publications
- A. Abdelaal, J. G. Kauffman, M. Dalla Longa, F. Conzatti and M. Ortmanns
An 80 MHz CT DSM With SMASH DAC Achieving 106.2 dB SFDR Without Linearity Calibration
IEEE Journal of Solid-State Circuits, Dez. 2025.
DOI: 10.1109/JSSC.2025.3648344
- Zaky, B.; Kauffman, J. G.; Conzatti, F.; Ortmanns, M.
Non-Linearity Cancellation of Gm-C Based DSM
IEEE International Symposium on Circuits and Systems (ISCAS), London, United Kingdom, Juni 2025
DOI: 10.1109/ISCAS56072.2025.11044033
- A. Abdelaal, J. G. Kauffman, J. Becker, M. Dalla Longa, F. Conzatti and M. Ortmanns
A Calibration-free 80MHz CT DSM Using Dual Quantization and ISI Shuffler Achieving 106.2dB SFDR
IEEE Custom Integrated Circuits Conference (CICC), Boston, MA, USA, Apr. 2025.
DOI: 10.1109/CICC63670.2025.10982928