Room: 43.2.408
Tel.: +49 (0)731 - 50 26210
nicolas.graber(at)uni-ulm.de
M.Sc. Nicolas Graber
Nicolas Graber received his B.Sc. and M.Sc. degrees in Electrical Engineering from the University of Ulm in 2021 and 2024, respectively. For his bachelor thesis and as a student research assistant, he worked on neural interfaces and high-speed delta-sigma ADCs. For his master thesis, he designed and implemented an artifact-tolerant neural recording front-end with direct analog-to-digital conversion.
From April to September 2023, he worked as an analog design intern in the analog and mixed-signal department at Qualcomm Technologies Inc. (Cork, Ireland). In August 2024, he joined the Institute of Microelectronics to pursue his Ph.D. under the supervision of Prof. Dr.-Ing. Maurits Ortmanns. His current research interest is in the field of artifact-tolerant neural recording.
Student theses
[mt] = Master thesis, [rp] = Bachelor thesis
Current theses
- Ilona Roch
Development of a Graphical User Interface for a Wireless Neuromodulation System [rp] - Lena Barth
Development of a Central Communication Hub for a Wireless Neural Recording System [rp] - Nick Hertsch
Development of a Performant FPGA-Based ADC Measurement Setup with Live Data Transmission [rp]
Publications
2025
A Wireless Headstage Based on a 32-Channel Neuromodulator Integrated Circuit
IEEE International Symposium on Circuits and Systems (ISCAS), London, United Kingdom
May 2025
DOI: | 10.1109/ISCAS56072.2025.11043699 |
2024
An ultra-miniaturized Neural Recording μASIC for the NeuroBus Implant
IEEE Biomedical Circuits and Systems Conference (BioCAS), Xi'an, China, pp. 1-5
December 2024
DOI: | 10.1109/BioCAS61083.2024.10798303 |
NeuroBus - Architecture for an Ultra-Flexible Neural Interface
IEEE Transactions on Biomedical Circuits and Systems ( Early Access ), Pages: 1 - 16
January 2024
DOI: | 10.1109/TBCAS.2024.3354785 |
2023
NeuroBus – Architecture and Communication Bus for an Ultra-Flexible Neural Interface
IEEE International Symposium on Circuits and Systems (ISCAS), Monterey, CA, USA
May 2023
DOI: | 10.1109/ISCAS46773.2023.10181816 |
2021
Implementation of a Low Power Decimation Filter in a 180 nm HV-CMOS Technology for a Neural Recording Front-End
SMACD / PRIME 2021; International Conference on SMACD and 16th Conference on PRIME, pp. 1-4.
July 2021
Research Assistent
