The linearity of the Digital-to-Analog converter (DAC) plays an important role in the performance of the Sigma-Delta Analog-to-Digital Converter (ADC), two main errors affect the DACs linearity:
- Dynamic errors
- Static errors
Literature proposed different technique to average out/high pass filter (shape) such errors (e.g. Dynamic element matching, Data weighted Averaging and Intersymbol interference shaping techniques). The aim of this project is to investigate the feasibility of implementation of these techniques (delay as well as performance at low over sampling ratios (OSR)), given the ADC specification in terms of number of quantization bits.
The tools to be use are:
- Cadence Virtuoso
- Genus/Innovus
- Matlab
What we expect:
- Knowledge about basic mixed signal circuits
- Knowledge about Verilog/VHDL
- Organized and documented work