Correct data read out from an Analog-to-Digital Converter is critical for characterizing the ADC. Especially for High speed ADCs, where the clock frequency is in the Giga-Hertz range. Clock and Data synchronization is essential for the performance of the ADC; because clock-data skew would result in bit errors and affect the signal to noise ratio of the modulator.
The aim of this project is to design and test setup for ADCs. This includes data acquisition from the ADC using GT-transceivers, followed by some data storage/processing on the FPGA, and lastly sending the data to PC via Ethernet. A final task would be to create parameters based scripts to allow modification of the measurement setup for different ADC specifications.
The tools to be use are:
- Xilinx
- Altium
What we expect:
- Knowledge about Verilog/VHDL
- Organized and documented work