High-speed data acquisition systems, and broadband communication systems require high-speed analog to digital converters (ADCs). In the state of the art, time-interleaved ADC (TI-ADC) are the most prominent candidates to improve the bandwidth and sampling rate by time-interleaving multiple ADC channels. Fig. 1 shows the simplified idea of a time-interleaved ADC.
On the other hand, noise-shaping and oversampled converters like the Delta Sigma ADCs are known for their power efficiency while achieving high resolution.
Unfortunatley, Delta Sigma ADCs have memory and filter the input signal, such that they can not be directly used in a TI ADC.
Goals (extent depending on bachelor or master thesis):
- Build Matlab & Simulink model for various time-interleaved Delta Sigma ADC architectures using continuous-time loop filters.
- Investigate the effects of the non-idealities by simulation and theory.
- Build behavioral-model for the system using Cadence and VerilogA-based analog hardware description & determine the specification of each sub-block in the system.
What we expect:
- Good skills in Matlab and Simulink and knowledge about data converters.
- Cadence skills and knowledge about analog IC design desirable.
- Organized and well documented research and dedication to successful work.