Institute of Microelectronics

Power-Efficient Deep Neural Networks based on Co-Optimization with Mixed-Signal Integrated Circuits

EdgeAI is the distributed computing paradigm for executing machine-learning algorithms close to the sensor. Compared to centralized, e.g. cloud-based solutions, data security, low latency and bandwidth reduction are achieved. At the same time, there is the major problem that the power consumption of today's deep neural networks (the most common kind of machine-learning algorithm) is far too high for such applications. Modern network architectures are complex and place high demands on computing resources. This problem is addressed in two ways.

First, the compute effort of the neural network can be reduced by pruning or quantizing operands. This is commonly referred to as network compression.

A second way of enabling deployment of AI algorithms at the Edge is the use of specialized accelerators (processors) to overcome a common problem: AI algorithms typically require huge amounts of data being moved between memory and computation. This problem is referred to as von Neumann Bottleneck. The solution is to simply distribute and mix compute and memory elements within the accelerator’s architecture.

This project investigates various aspects, in which optimization of hardware and algorithm need to be treated as a joint problem. The regarded hardware platforms are mixed-signal accelerators, which use analog quantities (charge, voltage, current) to represent operands within an AI computation.

[Translate to English:] Nonlinearity Modeling for Mixed-Signal Inference Accelerators in Training Frameworks
J. Conrad, B. Jiang, P. Kässer, V. Belagiannis and M. Ortmanns, "Nonlinearity Modeling for Mixed-Signal Inference Accelerators in Training Frameworks," 2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS), Dubai, United Arab Emirates, 2021, pp. 1-4, doi: 10.1109/ICECS53924.2021.9665503.

An example of such a problem is analog non-idealities within the mixed-signal computing circuits. They can be reduced by improving the circuit, but this comes with disadvantages in terms of performance, area and/or speed of the hardware. On the other hand, non-idealities can be modeled when training a neural network to minimize their impact on the inference result.

In this project, both approaches will be studied and aligned in parallel. The optimization of the neural networks is based on simulated and measured hardware specifications, while the optimized neural networks significantly increase the efficiency of the implemented hardware.

Future work will implement additional hardware to obtain extensive measurement results, allowing even more detailed rules for hardware and algorithm co-design to be derived. This should open up new possibilities for the use of AI algorithms close to the terminal (EdgeAI).

Publications

  1. Conrad, J.; Wilhelmstätter, S.; Mandry, H.; Kässer, P.; Abdelaal, A.; Asthana, R.; Belagiannis, V.; Ortmanns, M.
    PSumSim: A Simulator for Partial-Sum Quantization in Analog Matrix-Vector Multipliers
    IEEE International Symposium on Circuits and Systems (ISCAS), London, United Kingdom
    Mai 2025
    DOI: 10.1109/ISCAS56072.2025.11043442
     
  2. Conrad, J.; Wilhelmstätter, S.; Asthana, R.; Belagiannis, V.; Ortmanns, M.
    Differentiable Cost Model for Neural-Network Accelerator Regarding Memory Hierarchy
    IEEE Transactions on Circuits and Systems I: Regular Papers ( Early Access )
    Oktober 2024
    DOI: 10.1109/TCSI.2024.3476534
     
  3. Conrad, J.; Kauffman, J. G.; Wilhelmstätter, S.; Asthana, R.; Belagiannis, V.; Ortmanns, M.
    Confidence Estimation and Boosting for Dynamic-Comparator Transient-Noise Analysis
    22nd IEEE Interregional NEWCAS Conference (NEWCAS)
    September 2024
    DOI: 10.1109/NewCAS58973.2024.10666354
     
  4. Conrad, J.; Jiang, B.; Kässer, P.; Belagiannis, V.; Ortmanns, M.
    Nonlinearity Modeling for Mixed-Signal Inference Accelerators in Training Frameworks
    28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS), Dubai, UAE, 2021, pp. 1-4
    DOI: 10.1109/ICECS53924.2021.9665503
     
  5. Conrad, J.; Wilhelmstätter, S.; Asthana, R.; Belagiannis, V.; Ortmanns, M.
    Too-Hot-to-Handle: Insights into Temperature and Noise Hyperparameters for Differentiable Neural-Architecture-Searches
    6th IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS), Abu-Dhabi, UAE, 2024, pp. 557-561
    DOI: 10.1109/AICAS59952.2024.10595971