Circuit Design in Nanometre-Scale CMOS Technologies
Module Description
In this module, we will introduce key challenges associated with designing using nanometre-scale CMOS design technologies. The course begins by reviewing the limitations of the square-law model and how it breaks down in nanometre-scale design. The advanced charge-based model is introduced to address this shortcoming, providing a new perspective on designing with short-channel effects. After reviewing the operating regions of the MOSFET, we will further examine thermal and 1/f noise effects, taking into account the newly introduced modelling. After exploring various layout techniques, the course continues with the design of single-stage amplifiers and an investigation of different output stages and their effects on performance. Both single-ended and differential topologies will be discussed, whilst delving further into more complex compensation techniques, leading to an introduction to multi-stage/multipath operational amplifier design. To conclude the course, we review operational amplifier stability metrics and explore advanced test benches that incorporate parasitic loading, enabling stable systems at low power and/or high speed.
Module Contents
- MOSFET operation and modern CMOS devices
- Short-channel and narrow-channel effects in advanced nm CMOS technologies
- Advanced noise modelling
- Layout and matching techniques
- Single-stage op-amp design
- Multi-stage op-amp design
- Fully-differential op-amps
- Stability and Op-amp Testbenches
- State-of-the-art design examples