Theses

[rp] = Bachelorarbeit, [mt] = Masterarbeit

1. Hannes Müller
   Analysis and Design of a Continous-Time Linear- Exponential Incremental Analog-to-Digital Converter [mt]
   Tutor: Elias Ruopp
   Prof. Dr.-Ing. Maurits Ortmanns
2. Manuel Elia
   Analysis and Implementation of a Matched Loop Filter for a Continuous-Time Incremental Delta-Sigma ADC [rp]
   Tutor: Elias Ruopp
   Prof. Dr.-Ing. Maurits Ortmanns
3. Salma Mohamed
   Design and Implementation of a Continuous-Time Linear-Exponential Incremental Delta-Sigma ADC [mt]
   Tutor: Elias Ruopp
   Prof. Dr.-Ing. Maurits Ortmanns
4. Lukas Rumpel
   Advanced FPGA (VHDL) based Digital Control-Loop Development for Space [mt]
   Dr. Lamour, Tobias, Airbus Defence & Space
   Prof. Dr.-Ing. Maurits Ortmanns