Publikationen (Gesamt)
2021
570.
Sporer,
M.;
Graber,
N.;
Moll,
S.;
Reich,
S.;
Ortmanns,
M.
Implementation of a Low Power Decimation Filter in a 180 nm HV-CMOS Technology for a Neural Recording Front-End
SMACD / PRIME 2021; International Conference on SMACD and 16th Conference on PRIME, pp. 1-4.
Juli 2021
Implementation of a Low Power Decimation Filter in a 180 nm HV-CMOS Technology for a Neural Recording Front-End
SMACD / PRIME 2021; International Conference on SMACD and 16th Conference on PRIME, pp. 1-4.
Juli 2021
569.
Müelich,
S.;
Mandry,
H.;
Ortmanns,
M.;
Fischer,
R.
A Multilevel Coding Scheme for Multi-Valued Physical Unclonable Functions
IEEE Transactions on Information Forensics and Security
Juni 2021
A Multilevel Coding Scheme for Multi-Valued Physical Unclonable Functions
IEEE Transactions on Information Forensics and Security
Juni 2021
| DOI: | 10.1109/TIFS.2021.3089883 |
568.
Ezekwe,
C.;
Ganta,
S.;
Xing,
X.;
Grad,
A.;
Mayer,
T.;
Visconti,
A.;
Diazzi,
F.;
Chen,
M.;
Morton,
D.;
Valli,
L.;
Wolf,
R.;
Eghtesadi,
A.;
Wolfer,
T.;
Pietzko,
M.;
Grathwohl,
A.;
Northemann,
T.;
Schoenleber,
R.;
Khalilyulin,
R.;
Mukhopadhyay,
I.;
Negut,
A.;
Kosov,
A.;
Serafin,
A.;
Hayek,
J.;
Sun,
L.
A direct-digitization open-loop gyroscope frontend with +/-8000°/s full-scale range and noise floor of 0.0047°/s/√Hz
Symposium on VLSI Circuits, 2021, pp. 1-2
Juni 2021
A direct-digitization open-loop gyroscope frontend with +/-8000°/s full-scale range and noise floor of 0.0047°/s/√Hz
Symposium on VLSI Circuits, 2021, pp. 1-2
Juni 2021
| DOI: | 10.23919/VLSICircuits52068.2021.9492404 |
567.
Reich,
S.;
Sporer,
M.;
Ortmanns,
M.
A Chopped Neural Front-end featuring Input Impedance Boosting with suppressed offset-induced charge transfer
IEEE Transactions on Biomedical Circuits and Systems
Mai 2021
A Chopped Neural Front-end featuring Input Impedance Boosting with suppressed offset-induced charge transfer
IEEE Transactions on Biomedical Circuits and Systems
Mai 2021
| DOI: | 10.1109/TBCAS.2021.3080398 |
566.
Abdelaal,
A.;
Pietzko,
M.;
Mokhtar,
M. A.;
Kauffman,
J. G.;
Ortmanns,
M.
FIR filter with Symmetric Non-Equal Coefficients for CT Delta-Sigma Modulators
IEEE International Symposium on Circuits and Systems (ISCAS), Daegu, Korea (Online)
Mai 2021
FIR filter with Symmetric Non-Equal Coefficients for CT Delta-Sigma Modulators
IEEE International Symposium on Circuits and Systems (ISCAS), Daegu, Korea (Online)
Mai 2021
565.
Pietzko,
M.;
Wagner,
J.;
Abdelaal,
A.;
Kauffman,
J. G.;
Ortmanns,
M.
Influence of Excess Loop Delay on the STF of Continuous-Time Delta-Sigma Modulators
IEEE International Symposium on Circuits and Systems (ISCAS), Daegu, Korea (Online)
Mai 2021
Influence of Excess Loop Delay on the STF of Continuous-Time Delta-Sigma Modulators
IEEE International Symposium on Circuits and Systems (ISCAS), Daegu, Korea (Online)
Mai 2021
564.
Mandry,
H.;
Müelich,
S.;
Becker,
J.;
Fischer,
R.;
Ortmanns,
M.
Using Polynomial Interpolation for Reproducing Multi-Valued Responses of Physical Unclonable Functions on FPGAs
IEEE International Symposium on Circuits and Systems (ISCAS)
Mai 2021
Using Polynomial Interpolation for Reproducing Multi-Valued Responses of Physical Unclonable Functions on FPGAs
IEEE International Symposium on Circuits and Systems (ISCAS)
Mai 2021
| DOI: | 10.1109/ISCAS51556.2021.9401501 |
563.
Mokhtar,
M. A.;
Abdelaal,
A.;
Sporer,
M.;
Becker,
J.;
Kauffman,
J. G.;
Ortmanns,
M.
A 0.9-V Calibration-Free 97dB-SFDR 2-MS/s ContinuousTime Incremental Delta-Sigma ADC Utilizing Variable Bit-Width Quantizer in 28nm CMOS
IEEE Custom Integrated Circuits Conference (CICC), Texas, USA (Virtual)
April 2021
A 0.9-V Calibration-Free 97dB-SFDR 2-MS/s ContinuousTime Incremental Delta-Sigma ADC Utilizing Variable Bit-Width Quantizer in 28nm CMOS
IEEE Custom Integrated Circuits Conference (CICC), Texas, USA (Virtual)
April 2021
562.
Rajabzadeh,
M.;
Ungethüm,
J.;
Herkle,
A.;
Schilpp,
C.;
Becker,
J.;
Fauler,
M.;
Wittekindt,
O.;
Frick,
M.;
Ortmanns,
M.
A PCB Based 24-Ch. MEA-EIS Allowing Fast Measurement of TEER
IEEE Sensor Journal
März 2021
A PCB Based 24-Ch. MEA-EIS Allowing Fast Measurement of TEER
IEEE Sensor Journal
März 2021
| DOI: | 10.1109/JSEN.2021.3067823 |
561.
Haas,
M.;
Ortmanns,
M.
Neural Stimulation Circuits
Herausgeber: River Publishers
Selected Topics in Biomedical Circuits and Systems, Eds Minkyu Je and Myung Hoon Sunwoo Edition
Februar 2021
Neural Stimulation Circuits
Herausgeber: River Publishers
Selected Topics in Biomedical Circuits and Systems, Eds Minkyu Je and Myung Hoon Sunwoo Edition
Februar 2021
| ISBN: | 9788770221481 |
560.
Luo,
Y.;
Ortmanns,
M.
Input Referred Noise of VCO-Based Comparators
IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 68, no. 1, pp. 82-86
Januar 2021
Input Referred Noise of VCO-Based Comparators
IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 68, no. 1, pp. 82-86
Januar 2021
| DOI: | 10.1109/TCSII.2020.3008260 |
559.
Conrad,
J.;
Jiang,
B.;
Kässer,
P.;
Belagiannis,
V.;
Ortmanns,
M.
Nonlinearity Modeling for Mixed-Signal Inference Accelerators in Training Frameworks
28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS), pp. 1-4
2021
Nonlinearity Modeling for Mixed-Signal Inference Accelerators in Training Frameworks
28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS), pp. 1-4
2021
| DOI: | 10.1109/ICECS53924.2021.9665503 |
2020
558.
Wagner,
J.;
Vogelmann,
P.;
Ortmanns,
M.
An Automated Design Environment for CT Incremental Sigma-Delta ADCs
27th IEEE International Conference on Electronics, Circuits and Systems (ICECS)
November 2020
An Automated Design Environment for CT Incremental Sigma-Delta ADCs
27th IEEE International Conference on Electronics, Circuits and Systems (ICECS)
November 2020
557.
Abdelaal,
A.;
Kauffman,
J. G.;
Mokhtar,
M. A.;
Ortmanns,
M.
A Comparative Study of ISI Errors in Different DAC Structures for CT Delta-Sigma Modulators
IEEE International Symposium on Circuits and Systems (ISCAS), Sevilla, Spain
Oktober 2020
A Comparative Study of ISI Errors in Different DAC Structures for CT Delta-Sigma Modulators
IEEE International Symposium on Circuits and Systems (ISCAS), Sevilla, Spain
Oktober 2020
556.
Reich,
S.;
Sporer,
M.;
Ortmanns,
M.
A self-compensated, low-offset Voltage Buffer for Input Impedance Boosting in Chopped Neural Front-ends
IEEE International Symposium on Circuits and Systems (ISCAS), Seville, Spain
Oktober 2020
A self-compensated, low-offset Voltage Buffer for Input Impedance Boosting in Chopped Neural Front-ends
IEEE International Symposium on Circuits and Systems (ISCAS), Seville, Spain
Oktober 2020
555.
Herkle,
A.;
Rossak,
P.;
Mandry,
H.;
Becker,
J.;
Ortmanns,
M.
Comparison of measurement and readout strategies for RO-PUFs on Xilinx Zynq-7000 SoC FPGAs
IEEE International Symposium on Circuits and Systems (ISCAS), Seville, Spain
Oktober 2020
Comparison of measurement and readout strategies for RO-PUFs on Xilinx Zynq-7000 SoC FPGAs
IEEE International Symposium on Circuits and Systems (ISCAS), Seville, Spain
Oktober 2020
554.
Herkle,
A.;
Mandry,
H.;
Becker,
J.;
Reich,
S.;
Sporer,
M.;
Ortmanns,
M.
Extracting Weak PUFs from Differential Nonlinearity of Digital-to-Analog Converters
IEEE International Symposium on Circuits and Systems (ISCAS), Seville, Spain
Oktober 2020
Extracting Weak PUFs from Differential Nonlinearity of Digital-to-Analog Converters
IEEE International Symposium on Circuits and Systems (ISCAS), Seville, Spain
Oktober 2020
553.
Mokhtar,
M. A.;
Vogelmann,
P.;
Abdelaal,
A.;
Kauffman,
J. G.;
Ortmanns,
M.
FIR DACs in CT Incremental Delta-Sigma Modulators
IEEE International Symposium on Circuits and Systems (ISCAS), Sevilla, Spain
Oktober 2020
FIR DACs in CT Incremental Delta-Sigma Modulators
IEEE International Symposium on Circuits and Systems (ISCAS), Sevilla, Spain
Oktober 2020
552.
Herkle,
A.;
Mandry,
H.;
Becker,
J.;
Ortmanns,
M.
Live Demonstration: Generating FPGA Fingerprints utilizing Full-Chip Characterization with Ring-Oscillator PUFs
IEEE International Symposium on Circuits and Systems (ISCAS), Seville, Spain
Oktober 2020
Live Demonstration: Generating FPGA Fingerprints utilizing Full-Chip Characterization with Ring-Oscillator PUFs
IEEE International Symposium on Circuits and Systems (ISCAS), Seville, Spain
Oktober 2020
551.
Vogelmann,
P.;
Wagner,
J.;
Ortmanns,
M.
A 14b, Twofold Time-Interleaved Incremental ΔΣ ADC Using Hardware Sharing
IEEE Transactions on Circuits and Systems I: Regular Papers
Juli 2020
A 14b, Twofold Time-Interleaved Incremental ΔΣ ADC Using Hardware Sharing
IEEE Transactions on Circuits and Systems I: Regular Papers
Juli 2020
| DOI: | 10.1109/TCSI.2020.3011362 |
550.
Rajabzadeh,
M.;
Häberle,
M.;
Becker,
J.;
Ortmanns,
M.
Comparison Study of DAC Realizations in Current Input CTΣΔ Modulators
IEEE Transactions on Circuits and Systems II: Express Briefs
Juli 2020
Comparison Study of DAC Realizations in Current Input CTΣΔ Modulators
IEEE Transactions on Circuits and Systems II: Express Briefs
Juli 2020
| DOI: | 10.1109/TCSII.2020.3007964 |
549.
Conrad,
J.;
Vogelmann,
P.;
Mokhtar,
M. A.;
Ortmanns,
M.
Design Approach for Ring Amplifiers
IEEE Transactions on Circuits and Systems I: Regular Papers
April 2020
Design Approach for Ring Amplifiers
IEEE Transactions on Circuits and Systems I: Regular Papers
April 2020
| DOI: | 10.1109/TCSI.2020.2986553 |
548.
Wagner,
J.;
Vogelmann,
P.;
Ortmanns,
M.
Performance Evaluation of Incremental Sigma-Delta ADCs Based on their NTF
IEEE Transactions on Circuits and Systems—II: Express Briefs (Early Access)
März 2020
Performance Evaluation of Incremental Sigma-Delta ADCs Based on their NTF
IEEE Transactions on Circuits and Systems—II: Express Briefs (Early Access)
März 2020
547.
Mandry,
H.;
Herkle,
A.;
Müelich,
S.;
Becker,
J.;
Fischer,
R.;
Ortmanns,
M.
Normalization and Multi-Valued Symbol Extraction from RO-PUFs for Enhanced Uniform Probability Distributions
IEEE Transactions on Circuits and Systems--II: Express Briefs
März 2020
Normalization and Multi-Valued Symbol Extraction from RO-PUFs for Enhanced Uniform Probability Distributions
IEEE Transactions on Circuits and Systems--II: Express Briefs
März 2020
| DOI: | 10.1109/TCSII.2020.2980748 |
546.
Qi,
L.;
Jain,
A.;
Jiang,
D.;
Sin,
S.-W.;
Martins,
R. P.;
Ortmanns,
M.
A 76.6-dB-SNDR 50-MHz-BW 29.2-mW Multi-Bit CT Sturdy MASH With DAC Non-Linearity Tolerance
IEEE Journal of Solid-State Circuits
Februar 2020
A 76.6-dB-SNDR 50-MHz-BW 29.2-mW Multi-Bit CT Sturdy MASH With DAC Non-Linearity Tolerance
IEEE Journal of Solid-State Circuits
Februar 2020
| DOI: | 10.1109/JSSC.2019.2942359 |