Publikationen_Bearbeitung

Artikel

124.
Schreier, R.; Rothermel, A.
Latenzzeitoptimierte Videokompression
FKTG Jahrestagung, Potsdam
2006
123.
Schreier, R.; Rothermel, A.
Motion Adaptive Intra Refresh for Low-Delay Video Coding
Digest of Technical Papers IEEE International Conference on Consumer Electronics (ICCE), pp. 453-454
2006
122.
Schreier, R.; Rothermel, A.
Motion adaptive intra refresh for the H.264 video coding standard
IEEE Transactions on Consumer Electronics, Vol. 52, No. 1, pp. 249-253
2006
121.
Henrici, F.; Becker, J.; Manoli, Y.
Simulation eines rekonfigurierbaren Gm-C Filter Arrays
Kleinheubacher Berichte - Advances in Radio Science, Miltenberg, Germany
2006
120.
Henrici, F.; Becker, J.; Manoli, Y.
Simulation of a reconfigurable mixed-signal Field Programmable Analog Array
Technical talk at CDNLive! EMEA, Nice, France
2006
119.
Becker, J.; Manoli, Y.
Synthesis of analog filters on a continuous-time FPAA using a genetic algorithm
in Proc. IEEE International Conference on Field Programmable Logic (FPL), Madrid
2006
118.
Becker, J.; Manoli, Y.
Visualisierung analoger Schaltungen durch 3D Animation von transienten SPICE-Simulationen
in Proc. Advances in Radio Science, Miltenberg, Germany
2006
117.
Zahabi, A.; Shoaei, O.; Koolivand, Y.; Jabehdar-maralani, P.
A Low-Power Sigma-Delta Modulator with Low Capacitor Spread for Multi-Standard Receiver Applications
International Symp. on Circuits and Systems (ISCAS) , pp. 3231–3234, Kobe (Japan)
Mai 2005
116.
Koolivand, Y.; Shoaei, O.; Zahabi, A.; Shamsi, H.; Jabehdar-maralani, P.
A New Technique for Design CMOS LNA for Multi-Standard Receivers
International Symp. on Circuits and Systems (ISCAS), pp. 3231-3234, Kobe (Japan)
Mai 2005
115.
Zahabi, A.; Shoaei, O.; Koolivand, Y.; Jabehdar-maralani, P.
A 2/5 mW CMOS DS Modulator Employed in an Improved GSM/UMTS Receiver Structure
IEICE Electron. Express, Vol.2, No.8, pp. 267-273
April 2005
114.
Ortmanns, M.; Gerfers, F.; Manoli, Y.
A Case Study On A 2-1-1 Cascaded Continuous-Time Sigma-Delta Modulator
IEEE Trans. on Circuits and Systems I, Vol.52, No.8, pp. 1515-1525
2005
113.
Ortmanns, M.; Gerfers, F.; Manoli, Y.
A Continuous-Time Sigma-Delta Modulator with Reduced Sensitivity to Clock Jitter through SCR-feedback
IEEE Trans. on Circuits and Systems I, Vol.52, No.5, pp. 875-884
2005
112.
Ortmanns, M.; Gerfers, F.; Manoli, Y.
Increased Jitter Sensitivity in Continuous- and Discrete-Time Sigma-Delta Modulators due to finite OpAmp Settling Speed
IEEE Int. Symp. on Circuits and Systems (ISCAS), Kobe, Japan
2005
111.
Koolivand, Y.; Shoaei, O.; Zahabi, A.; Jabehdar-maralani, P.
A Complete Analysis of Noise in Inductively Source Degenerated CMOS LNA’s
IEICE Electron. Express, Vol.2, No.1, pp. 25-31
Januar 2005
110.
Zahabi, A.; Shoaei, O.; Koolivand, Y.; Jabehdar-maralani, P.
A Two-Stage Genetic Algorithm Method for Optimization the Δ∑ Modulators
In Proc. of IEEE Asia South Pacific Design Automated Conference (ASP-DAC), Vol. 2, pp. 1212-1215, Shanghai (China), January
2005
109.
Zahabi, A.; Shoaei, O.; Koolivand, Y.; Jabehdar-maralani, P.
A Δ∑ Modulator with Low Power Consumption and Low Capacitor Spread for GSM/UMTS Receiver
In Proc. of Iranian Conference On Electrical Engineering (ICEE), pp. 531–536, Zanjan (Iran), April
2005
108.
Afzal, B.; Zahabi, A.; Amirabadi, A.; Koolivand, Y.; Afzali-Kusha, A.; El Nokali, M.
Analytical Model for C–V Characteristic of Fully Depleted SOI–MOS Capacitors
Solid State Electronics (SSE),Vol. 49, Issue 8, pp. 1262-1273, August
2005
107.
Zahabi, A.; Shoaei, O.; Koolivand, Y.
Design of a Band-pass Pseudo-2-path Switched Capacitor Ladder Filter
In Proc. of International Symposium on Quality Electronic Design (ISQED), pp. 662–667, San Jose (CA USA), March
2005
106.
Zhang, C.; Günter, Ch.; Rothermel, A.
Hardware Implementation of an Entropy Encoder for JPEG2000
Austrochip, Vienna, Austria
2005
105.
Tischler, K.; Clauss, M.; Guenter, Y.; Kaempchen, N.; Schreier, R.; Stiegeler, M.
Networked environment description for advanced driver assistance systems
Intelligent Transportation Systems, Proceedings IEEE, Page(s):785 - 790
2005
104.
Becker, J.; Henrici, F.; Manoli, Y.
Rekonfigurationstechniken und Anwendungsgebiete für ein programmierbares Gm-C Analog-Filter
in Proc. Advances in Radio Science, Miltenberg, Germany
2005
103.
Becker, J.; Henrici, F.; Manoli, Y.
System-Level Analog Simulation of a Mixed-Signal Continuous-Time Field Programmable Analog Array
in Proc. IEEE International Workshop System-on-Chip for Real-Time Applications (IWSOC), pp. 434-438, Banff
2005
102.
Kaempchen, N.; Clauss, M.; Guenter, Y.; Schreier, R.; Stiegeler, M.; Tischler, K.; Dietmayer, A.; Grossmann, H.-P.; Kabza, H.; Rothermel, A.; Stiller, C.; Neumann, H.
Vernetzte Fahrzeug-Umfelderfassung für zukünftige Fahrerassistenzsysteme
Fahrerassistenz-Workshop, Walting, Germany
2005
101.
Mou, D.; Schweer, R.; Rothermel, A.
Automatic Databases for Unsupervised Face Recognition.
1st IEEE Workshop on Face Processing in Video (FPIV’04), Washington D.C. (in: Proceedings of the IEEE International Conference on Computer Vision and Pattern Recognition (CVPR’04))
Juni 2004
100.
Mou, D.; Schweer, R.; Rothermel, A.
Automatic System for Recognition and Management of Persons.
21. Jahrestagung der Fernseh- und Kinotechnischen Gesellschaft FKTG, Koblenz (Session 10, Presentation 33)
Mai 2004
99.
Ortmanns, M.; Gerfers, F.; Kuderer, M.; Manoli, Y.
A Cascaded Continuous-Time Sigma-Delta Modulator with 80 dB Dynamic Range
IEEE Int. Symp. on Circuits and Systems (ISCAS), Vancouver, Canada
2004
98.
Ortmanns, M.; Gerfers, F.; Manoli, Y.
A New Technique for Automatic Error Correction in Sigma-Delta Modulators
IEEE Int. Symp. on Circuits and Systems (ISCAS), Kobe, Japan
2004
97.
Ortmanns, M.; Peters, C.; Manoli, Y.; Schmelzeisen, R.; Gutwald, R.
A Novel Method for in-vivo Stress Measurement in Osteosynthesis
Biomedizinische Technik BMT, Ilmenau, Germany
2004
96.
Becker, J.; Manoli, Y.
A Continuous-Time Field Programmable Analog Array (FPAA) consisting of digitally reconfigurable G_m-cells
in Proc. IEEE International Symposium on Circuits and Systems (ISCAS), I- 1092-5 Vol.1, Vancouver
2004
95.
Zahabi, A.; Shoaei, O.; Koolivand, Y.; Shamsi, H.
A Low-Power Programmable Low-Pass Switched Capacitor Filter Using Double Sampling Technique
IEEE International Conference on Microelectronics (ICM), pp. 651–654, Tunis (Tunisia), December
2004
94.
Becker, J.; Manoli, Y.
A new architecture of field programmable analog arrays for reconfigurable instantiation of continuous-time filters
in Proc. IEEE International Conference on Field-Programmable Technology (ICFPT), Brisbane, Australia
2004
93.
Ortmanns, M.; Peters, C.; Manoli, Y.; Schmelzeisen, R.; Gutwald, R.
A Pressure Sensor based in-vivo Stress Measurement in Osteosynthesis
Eurosensors XVIII, Rom, Italy
2004
92.
Shamsi, H.; Shoaei, O.; Zahabi, A.; Koolivand, Y.; Doost, R.
A Systematic Approach for Design of the IF and Base-Band of a Low-IF GSM Receiver
IEEE International Conference on Microelectronics (ICM), pp. 680–683, Tunis (Tunisia), December
2004
91.
Zahabi, A.; Shoaei, O.; Koo, Y.; Shamsi, H.
An Algorithmic Optimization Method for Design of Δ∑ Modulators
IEEE International Conference on Microelectronics (ICM), pp. 531–534, Tunis (Tunisia), December
2004
90.
Zahabi, A.; Koolivand, Y.; Afzali-Kusha, A.; Nourani, M.
Area and Power Optimization Method for High Speed Dual Vt Domino Logic with Noise Constraint
In Proc. of Iranian Conference on Electrical Engineering (ICEE), pp. 103–108, Mashad (Iran), May
2004
89.
Koolivand, Y.; Shoaei, O.; Zahabi, A.; Shamsi, H.; Atghiaee, A.
Design a Sixth-Order Switched Capacitor Pseudo-2-path Ladder Filter
In Proc. of Iranian Conference on Electrical Engineering (ICEE), pp.103–109, Mashad (Iran), May
2004
88.
Shamsi, H.; Shoaei, O.; Zahabi, A.; Koolivand, Y.; Doost, R.
Design Considerations of a High Frequency and Low Voltage Clock Generator
IEEE International Conference on Microelectronics (ICM), pp. 417–420, Tunis (Tunisia), December
2004
87.
Gerfers, F.; Ortmanns, M.; Manoli, Y.
Design issues and performance limitations of a clock jitter insensitive multibit DAC architecture for high-performance low-power CT sigma-delta modulators
IEEE Symposium on Circuits and Systems, Vancouver, Canada
2004
86.
Becker, J.; Manoli, Y.
Eine FPAA-Architektur zur rekonfigurierbaren Instantiierung von zeitkontinuierlichen Analogfiltern
in Proc. Advances in Radio Science, vol. 3, Issue 14, p.371-375, Miltenberg, Germany
2004
85.
Günter, Ch.; Schmidt, K.; Rothermel, A.; Pietsch, C.; Teich, W.
Hardware Realization of a Highly Flexible MIMO Demonstrator
9th International OFDM-Workshop, Dresden, Germany
2004
84.
Becker, M.; Lotze, N.; Becker, J.; Ortmanns, M.; Manoli, Y.
Implementation of a Power Optimized Decimator for Cascaded Sigma-Delta A/D Converters
IEEE International Conference on Signals and Electronic Systems (ICSES), Poznan, Poland
2004
83.
Becker, M.; Lotze, N.; Becker, J.; Ortmanns, M.; Manoli, Y.
Implementierung eines verlustleistungsoptimierten Dezimators für kaskadierte Sigma-Delta Analog-Digital Umsetzer
Advances in Radio Science Vol. 3 (Kleinheubacher Berichte 2004), pp. 389-393, Miltenberg, Germany
2004
82.
Schmidt, K.; Günter, Ch.; Rothermel, A.
Improving the Mobility of DVB Handheld Devices with Inter-Carrier Interference Compensation
IEEE International Symposium on Consumer Electronics, Reading, UK
2004
81.
Schmidt, K.; Günter, Ch.; Rothermel, A.
Low Complexity Inter-Carrier Interference Compensation for Mobile Reception of DVB-T
9th International OFDM-Workshop, Dresden, Germany
2004
80.
Shamsi, H.; Shoaei, O.; Zahabi, A.; Koolivand, Y.; Doost, R.
Low Power and Low Voltage Considerations in the Design of a High Frequency Clock Generator
In Proc. of IEEE Asia-Pacific Conference on Circuits and Systems (APCCAS), Vol. 2, pp. 933-936, Tainan (Taiwan) , December
2004
79.
Koolivand, Y.; Zahabi, A.; Masoumi, N.
Modeling of Polysilicide Gate Resistance Effect on Inverter Delay and Power Consumption Using Distributed RC Method and Branching Technique
In Proc. of Great Lakes Symposium on VLSI (GLSVLSI), pp. 149–153, Boston (MA USA), April
2004
78.
Keller, M.; Ortmanns, M.; Manoli, Y.
On the Implicit Anti-Aliasing Filter in Continuous Time Sigma Delta Modulators
IEEE International Conference on Signals and Electronic Systems (ICSES), Poznan, Poland
2004
77.
Albrecht, C.; Witte, P.; Kuehlmann, A.
Performance and Area Optimization using Sequential Flexibility
13th International Workshop on Logic and Synthesis, Temecula (California), USA, June
2004
76.
Mou, D.; Lares, R.; Yan, W.; Rominger, F.; Rothermel, A.
Design and Implementation of a Novel Sync Processing System for Composite Video Signals.
IEEE Trans. on Consumer Electronics, vol. 49, no. 4, pp. 1286-1291
November 2003
75.
Rothermel, A.; Lares, R.
Synchronization of Analog Video Signals with Improved Image Stability.
IEEE Trans. on Consumer Electronics, vol. 49, no. 4, pp. 1292-1300
November 2003
74.
Kumpf, T.; Müller-Schwanneke, C.; Jelonnek, B.; Splett, A.; Rothermel, A.
Optimization of an analog circuit using transistor level calibrated functional models
16th European Conference on Circuit Theory and Design, IEEE ECCTD'03, Krakau, Poland, pp. III 21-24
September 2003
73.
Ortmanns, M.; Gerfers, F.; Manoli, Y.
A Continuous-Time Sigma-Delta Modulator with Switched Capacitor Controlled Current Mode Feedback
European Solid-State Circuits Conference, Estoril, Portugal
2003
72.
Ortmanns, M.; Gerfers, F.; Manoli, Y.
Compensation of Finite Gain-Bandwidth Induced Errors in Continuous-Time Sigma-Delta Modulators
IEEE Int. Conf. on Electronics, Circuits and Systems, Sharjah, UAE
2003
71.
Ortmanns, M.; Gerfers, F.; Manoli, Y.
Ein zeitkontinuierlicher Sigma-Delta Modulator mit Stromquellen-Rückkopplung und reduzierter Clock-Jitter Empfindlichkeit
ITG/ GMM -Diskussionssitzung ANALOG03, Heilbronn, Germany
2003
70.
Ortmanns, M.; Gerfers, F.; Manoli, Y.
Fundamental Limits of Jitter Insensitivity in discrete and Continuous-Time Sigma-Delta Modulators
IEEE Int. Symp. on Circuits and Systems, Bangkok, Thailand
2003
69.
Ortmanns, M.; Gerfers, F.; Manoli, Y.
Influence of finite Integrator Gain Bandwidth on Continuous-Time Sigma-Delta Modulators
IEEE Int. Symp. on Circuits and Systems, Bangkok, Thailand
2003
68.
Ortmanns, M.; Gerfers, F.; Manoli, Y.
The implementation of a continuous-time sigma-delta modulator with reduced sensitivity to clock jitter
GMM/GI/ITG Fachtagung - Entwurf Integrierter Schaltungen und Systeme, E.I.S.-Workshop, Erlangen, Germany
2003
67.
Ortmanns, M.; Gerfers, F.; Manoli, Y.
The implementation of a continuous-time sigma-delta modulator with reduced sensitivity to clock jitter
GMM/GI/ITG Fachtagung - Entwurf Integrierter Schaltungen und Systeme, E.I.S.-Workshop, Erlangen, Germany
2003
66.
Gerfers, F.; Ortmanns, M.; Manoli, Y.
A 1.5-V, 12-bit Power-Efficient Continuous-Time Third-Order Sigma-Delta Modulator
IEEE Journal of Solid State Circuits, Vol.38, No.8, pp. 1343-1352
2003
65.
Gerfers, F.; Ortmanns, M.; Manoli, Y.
A 1V, 12-Bit Wideband Continuous-Time Sigma-Delta Modulator for UMTS Applications
IEEE Symposium on Circuits and Systems, Bangkok, Thailand
2003
64.
Becker, M.; Heiber, K.; Ortmanns, M.; Manoli, Y.
A Power Optimized Decimator Architecture for Cascaded Sigma-Delta Analog-to-Digital Converters
International Conference on Electronics, Circuits and Systems, Sharjah, UAE
2003
63.
Nguyen, H. N.; Rothermel, A.
Simplified Color Transformations for Analog Processing in CMOS Imagers
7th IEEE SCI (Systemics, Cybernetics and Informatics), 6 Seiten, nicht nummeriert, Orlando, Florida
2003
62.
Ortmanns, M.; Gerfers, F.; Manoli, Y.
A Continuous-Time Sigma-Delta Modulator with Reduced Jitter Sensitivity
European Solid-State Circuits Conference, Florence, Italy
2002
61.
Ortmanns, M.; Gerfers, F.; Samid, L.; Manoli, Y.
Multirate Cascaded Continuous-Time Sigma-Delta Modulators
IEEE Int. Symp. on Circuits and Systems, Phoenix, USA
2002
60.
Gerfers, F.; Hack, C.; Ortmanns, M.; Manoli, Y.
A 1.2V, 200µW Rail-to-Rail OpAmp with 90dB THD using Replica Gain Enhancement
European Solid-State Circuits Conference, Florence, Italy
2002
59.
Samid, L.; Gerfers, F.; Ortmanns, M.; Manoli, Y.
A new kind of low power multibit third order CT-lowpass modulator
IEEE Symposium on Circuits and Systems, Phoenix, USA
2002
58.
Schmidt, K.; Rothermel, A.
Antenna Diversity Systems for Mobile Analog TV-Receivers
IEEE International Symposium on Consumer Electronics 2000 (ISCE), erschienen im Theuberger Verlag Berlin, Proceedings ISCE 2002, S. F-83 - 87, Erfurt
2002
57.
Gerfers, F.; Soh, K. M.; Ortmanns, M.; Manoli, Y.
Figure of Merit based Design Strategy for Low-Power Continuous-Time Sigma-Delta Modulators
IEEE Symposium on Circuits and Systems, Phoenix, USA
2002
56.
Gerfers, F.; Ortmanns, M.; Samid, L.; Manoli, Y.
Implementation of a 1.5V Low-Power Clock-Jitter Insensitive Continuous-Time Sigma-Delta Modulator
IEEE Symposium on Circuits and Systems, Phoenix, USA
2002
55.
Kumpf, T.; Müller-Schwanneke, C.; Jelonnek, B.; Splett, A.; Rothermel, A.
Schnelle Simulation analoger Sigma-Delta-Modulatoren durch Abstraktion von Transistorschaltungen
VDE GI/ITG/GMM Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen", erschienen im Shaker-Verlag
2002
54.
Schreier, R.; Rothermel, A.; Schweer, R.
Verification and Evaluation of a Digital Video Data Slicer
IEEE ISCE, erschienen im Theuberger Verlag Berlin, Proceedings ISCE, S. E-75 - 80, Erfurt
2002
53.
Ortmanns, M.; Gerfers, F.; Manoli, Y.
Clock Jitter Insensitive Continous-Time Sigma-Delta Modulators
Int. Conf. on Electronics, Circuits and Systems, Sydney, Australia
2001
52.
Ortmanns, M.; Gerfers, F.; Manoli, Y.
On the Synthesis of Cascaded Continuous Time Sigma-Delta Modulators
V419-V422, IEEE Int. Symp. on Circuits and Systems, Sydney, Australia
2001
51.
Ortmanns, M.; Gerfers, F.; Samid, L.; Manoli, Y.
Successful Design of Cascaded Continous-Time Sigma-Delta Modulators
Int. Conf. on Electronics, Circuits and Systems, Malta
2001
50.
Ortmanns, M.; Gerfers, F.; Manoli, Y.
A 12 Bit Power Efficient Continuous-Time Sigma-Delta Modulator with 250?W Power Consumption
European Solid-State Circuits Conference, Villach, Austria
2001
49.
Langeheine, J.; Becker, J.; Fölling, S.; Meier, K.; Schemmel, J.
A CMOS FPTA Chip for Intrinsic Hardware Evolution of Analong Electronic Circuits
The Third NASA/DoD workshop on Evolvable Hardware
2001
48.
Becker, J.
Ein FPGA-basiertes Testsystem für gemischt analog/digitale ASICs
Diploma Thesis, Heidelberg
2001
47.
Lallinger, M.; Rothermel, A.
Gütekriterium für terrestrisch empfangene analoge Fernsehsignale
ITG/FKTG-Fachtagung "Elektronische Medien" erschienen im VDE-Verlag, ITG-Fachbericht 167, S. 241-244, Dortmund
2001
46.
Langeheine, J.; Becker, J.; Fölling, S.; Meier, K.; Schemmel, J.
Initial Studies of a New VLSI Field Programmable Transistor Array
Evolvable Systems: From Biology to Hardware, Proceedings of the Fourth International Conference (ICES)
2001
45.
Fuchs, G.; Wöhrle, P.; Teichner, D.; Rothermel, A.
Inter-Carrier-Interferenz durch nahe Reflexionen bei OFDM-Übertragungen in mobilen DVB-T Systemen
ITG/FKTG-Fachtagung "Elektronische Medien", erschienen im VDE-Verlag, ITG-Fachbericht 167, S. 213-216, Dortmund
2001
44.
Schmidt, K.; Lallinger, M.; Rothermel, A.
Mobiles Aufzeichnungssystem für terrestrisch empfangene analoge und digitale Fernsehsignale
ITG/FKTG-Fachtagung "Elektronische Medien", erschienen im VDE-Verlag, ITG-Fachbericht 167, S. 263-266, Dortmund
2001
43.
Lallinger, M.; Schmidt, K.; Rothermel, A.
Mobiles Aufzeichnungssystem für terrestrisch empfangene Fernsehsignale
Fachtagung Informationstechnik, S. 7-10, Magdeburg
2001
42.
Schreier, R.; Lallinger, M.; Rothermel, A.
MPEG-2 Codierung kritischer TV-Signale
Fachtagung Informationstechnik, S. 3-6, Magdeburg
2001
41.
Schreier, R.; Lallinger, M.; Teichner, D.; Rothermel, A.
MPEG-2 Encoding of Low-Quality TV Signals
IEEE Trans. on Consumer Electronics, vol. 47, no. 4, S. 853-857
2001
40.
Ortmanns, M.; Gerfers, F.; Manoli, Y.; Michel, A.; Meese, E.; Maas, R.
Direkte Detektion hybridisierter DNA auf der Oberfläche mikroelektronischer Chips
A. Wisser, W. Nachtigall (Eds.): BIONA-report 14, Akad. Wiss. Lit., Mainz, GTBB, Saarbrücken, pp. 184-187
2000
39.
Ortmanns, M.; Huang, X.; Manoli, Y.
Neue DAU-Rückkopplung für zeitkontinuierliche Sigma-Delta Modulatoren
Workshop Mikroelektronik für die Informationstechnik, VDE-ITG, pp. 221-226, Darmstadt, Germany
2000
38.
Lares, R.; Rothermel, A.
Sync signal processing for asynchronously sampled video signals
IEEE Int. Symposium on Circuits and Systems (ISCAS), S. III 575-578, Genf
2000
37.
Lares, R.; Graef, N.; Rothermel, A.
Synchronsignal-Filterung mit FIR-Filter und serieller, integrierter Koeffizientenberechnung
ITG/FKTG Fachtagung "Multimedia", erschienen im VDE-Verlag, ITG-Fachbericht 156, S. 251-256, Dortmund
1999
36.
Pfleiderer, H.-J.; Rothermel, A.
Emulationsboard für die JTAG-Test-Schnittstelle der Prozessorfamilie MSP430
Forum, München
1998
35.
Rau, M.; Oberst, T.; Lares, R.; Rothermel, A.; Schweer, R.; Menoux, N.
Clock/data recovery PLL using half-frequency clock
IEEE Journal of Solid-State Circuits, vol. 32, no. 7, S. 1156-1159
1997
34.
Lares, R.; Rothermel, A.; Schweer, R.
CMOS circuit technique for serial IC interconnection up to 1.1 Gb/s
European Solid-State Circuits Conference (ESSCIRC), S. 212-215, Southampton, UK
1997
33.
Rothermel, A.; Lares, R.
Decimation filtering for sigma-delta-modulated video signals
IEEE Int. Conf. On Consumer Electronics (ICCE), S. 428-429, Chicago
1997
32.
Pfleiderer, H.-J.; Rothermel, A.
Mikrokontroller und digitaler Signalprozessor rücken Zuckerkrankheit zu Leibe
Texas-Instruments-Datei
1997
31.
Lares, R.; Rothermel, A.
Synchronsignal-Aufbereitung für asynchron digitalisierte FBAS-Signale
ITG/FKTG-Fachtagung "Multimedia" erschienen im VDE-Verlag, ITG-Fachbericht 144, S. 363-366, Dortmund
1997
30.
Lares, R.; Rothermel, A.; Rau, M.; Schweer, R.
Taktrückgewinnung mittels Phasenregelschleife für NRZ-Datenübertragung mit 1GBit/s in CMOS-Technologie
GME-Fachtagung "Mikroelektronik", erschienen im VDE-Verlag, GME-Fachbericht 17, S. 187-194, München
1997
29.
Rau, M.; Oberst, T.; Lares, R.; Schweer, R.; Menoux, N.; Rothermel, A.
1 Gb/s clock recovery PLL in 0.5 mm CMOS
European Solid-State Circuits Conference (ESSCIRC), S. 68-71, Neuchâtel
1996
28.
Rau, M.; Rothermel, A.; Pfleiderer, H.-J.
Receiver with Constant Active Termination
Symposium on VLSI Circuits, Digest of Technical Papers pp. 140-141, Hawaii
1996
27.
Rau, M.; Rothermel, A.; Pfleiderer, H.-J.
Receiver with constant active termination
IEEE Symposium on VLSI Circuits, S. 140-141, Hawaii
1996
26.
Rothermel, A.; van de Plassche, R.
Introduction to the special issue
IEEE Journal of Solid-State Circuits, vol. 30, no. 7, S. 722-723
1995
25.
Rothermel, A.; Rau, M.; Schweer, R.; Blaud, P.
Störstrahlungsarme Digitalsignal-Übertragung
GME-Fachtagung "Mikroelektronik", erschienen im VDE-Verlag, GME-Fachbericht 15, S. 349-354, Baden Baden
1995
24.
Gillies, D.; Doty, J.; Rothermel, A.; Schweer, R.
Combined TV format control and sampling rate conversion IC
IEEE Int. Conf. on Consumer Electronics (ICCE), S. 332-333, Chicago, USA
1994
23.
Gillies, D.; Doty, J.; Rothermel, A.; Schweer, R.
Combined TV format control and sampling rate conversion IC
IEEE Trans. on Consumer Electronics, vol. 40, no. 3, S. 711-717
1994
22.
Rothermel, A.; Dell'ova, F.
Analog phase measuring circuit for digital CMOS-ICs
IEEE J. Solid-State Circuits, vol. 28, no. 7, pp. 853-856
1993
21.
Rothermel, A.; Dell'ova, F.
Analog phase measuring circuit for digital CMOS-ICs
European Solid-State Circuit Conference (ESSCIRC), Kopenhagen, pp 331-334
1992
20.
Rothermel, A.
Digitale Abtastratenkonversion im Fernsehempfänger
ITG-Fachtagung "Mikroelektronik für die Informationstechnik", erschienen im VDE-Verlag, ITG-Fachbericht 119, S. 153-158, Stuttgart
1992
19.
Rothermel, A.; Hirtz, G.
Konzepte für kompatible HDTV-Breitbildempfänger
VDE-Verlag Mikroelektronik, Bd. 6, Nr. 3, S. 154-157
1992
18.
Geiger, E. A.; Rothermel, A.; Westerkamp, D.
HDTV - Its impact on VLSI architecture and semiconductor technology
European Solid-State Circuits Conference (ESSCIRC), Invited Papers, S. 47-58, Invited Paper, Presentation: A. Rothermel, Milano
1991
17.
Tröster, G.; Sieber, P.; Schoppe, K.; Wedel, A.; Zocher, E.; Amdt, J.; Becker, T.; Dreßler, H.; Bergmann, H.; Goldberg, H.-J.; Hoppner, H.; Kling, H.; Schardein, W.; Rothermel, A.; Eßer, W.
A BiCMOS analog/digital array for cellular radio applications
IEEE Custom Integrated Circuits Conf., S. 12.6.1-12.6.4, Boston, USA
1990
16.
Tröster, G.; Eßer, W.; Rothermel, A.; Schardein, W.
BiCMOS "Sea of Gate"-Arrays
GME-Fachtagung "BiCMOS und Smart Power", erschienen im VDE-Verlag, GME-Fachberichte 6. S. 27-32, Bad Nauheim
1990
15.
Rothermel, A.; Eßer, W.; Hosticka, B.; Schardein, W.; Tröster, G.
BICMOS circuits for DPCM coders in HDTV systems
IEEE Internat. Solid-State Circuits Conf., S. 120-121, 278, San Francisco, USA
1990
14.
Rothermel, A.
BiCMOS circuits for DPCM coders in HDTV systems
IEEE Journal of Solid-State Circuits, vol. 25, no. 6, S. 1470-1475, auch als Nachdruck in: M. I. Elmasry, "BiCMOS integrated circuit design", IEEE press 1994, S. 216-221
1990
13.
Eßer, W.; Schardein, W.; Rothermel, A.; Tröster, G.
Konzepte für digitale Multiplizierer in BiCMOS-Technik
GME-Fachtagung "BiCMOS und Smart Power", erschienen im VDE-Verlag, GME-Fachberichte 6, S. 33-39, Bad Nauheim
1990
12.
Rothermel, A.; Zimmer, G.; Tröster, G.; Sieber, P.
BiCMOS-Schaltungen für die digitale Video-Signalverarbeitung
GME-Fachtagung "Mikroelektronik", erschienen im VDE-Verlag, GME-Fachbericht 4, S. 219-224, Baden Baden
1989
11.
Zimmer, G.; Eßer, W.; Fichtel, J.; Hosticka, B.; Rothermel, A.; Schardein, W.
BiCMOS: technology and circuit design
17th Yugoslav Conference on Microelectronics, MIEL, Nis, S. 505-513
1989
10.
Zimmer, G.; Eßer, W.; Fichtel, J.; Hosticka, B.; Rothermel, A.; Schardein, W.
BICMOS: technology and circuit design
Elsevier Microelectronics Journal, vol. 20, no. 1-2, S. 59-75
1989
9.
Rothermel, A.; Hosticka, B.; Tröster, G.; Arndt, J.
Realization of TGCS-adders (transmission-gate conditional-sum) with low latency time
IEEE Journal of Solid-State Circuits, vol. 24, no. 3, S. 558-561
1989
8.
Rothermel, A.; Hosticka, B.
Speed comparison of digital BICMOS and CMOS circuits
IEE Proceedings, vol. 136, pt. G, no. 2, S. 49-56
1989
7.
Tröster, G.; Sieber, P.; Tomaszewski, Z.; Fichtel, J.; Schardein, W.; Rothermel, A.; Hosticka, B.
Eine BiCMOS-Technologie zur Integration von Analog-Digitalsystemen
Kleinheubacher Tagung, Fernmeldetechnisches Zentralamt, Kleinheubacher Berichte Nr. 31, S. 57-63
1988
6.
Tröster, G.; Drusenthal, U.; Sieber, P.; Tomaszewski, Z.; Meier, W.; Rothermel, A.
Funktionsintegration komplexer Analog-Digitalsysteme mit der BiCMOS-Technik
ITG-Fachtagung "Mikroelektronik für die Informationstechnik", erschienen im VDE-Verlag, ITG-Fachbericht 103, S. 185-190, Berlin
1988
5.
Fichtel, J.; Rothermel, A.; Eßer, W.; Hosticka, B.; Schardein, W.
Grundlagen der analogen und digitalen Schaltungstechnik mit BiCMOS
VDE-Verlag Mikroelektronik, Bd. 2, Nr. 3, S. 108-112
1988
4.
Rothermel, A.; Hosticka, B.; Tröster, G.; Arndt, J.
Realization of conditional-sum adders with low latency time
European Solid-State Circuits Conference (ESSCIRC), Manchester, S. 350-353
1988
3.
Schardein, W.; Hosticka, B.; Rothermel, A.; Sieber, P.; Zimmer, G.
Konzepte für eine digitale gemischte bipolare CMOS-Schaltungstechnik (BiCMOS)
ITG-Fachtagung "Großintegration", erschienen im VDE-Verlag, ITG-Fachberichte 98, S. 163-166, Baden Baden
1987
2.
Rothermel, A.
Realization of a DPCM coder for 13.5-MHz sampling rate in CMOS technology
IEEE Journal of Solid-State Circuits, Vol. SC-22, no. 6, S. 1196-1197
1987
1.
Rothermel, A.; Hess, G.; Timmermann, D.; Wendt, H.
Entwurf und Realisierung eines Video-DPCM-Coders in CMOS-Technik
NTG-Fachtagung "Mikroelektronik für die Informationstechnik", erschienen im VDE-Verlag, NTG-Fachberichte 96, S. 287-292, Berlin
1986
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