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michael.pietzko(at)uni-ulm.de
M.Sc. Michael Pietzko
I studied electrical engineering at Saarland University, where I received my B.Sc. degree in October 2016. I continued my studies at the University of Ulm, where I received my M.Sc. degree in January 2020. From October 2018 to March 2019, I worked as an intern in the ASIC Design group at the Robert Bosch Research and Technology Center (Sunnyvale, CA). The topic of my Master thesis was ''Highly Linear Gm-C based Sigma Delta Modulator''.
In February 2020 I started working towards my Ph.D. degree at the Institute of Microelectronics at the University of Ulm under the supervision of Prof. Dr.-Ing. Maurits Ortmanns. My current research interest is in the field of ultra-low power continuous-time Sigma-Delta analog-to-digital converters.
Projects
Ultra-low Power, Wide Bandwidth Continuous-time Delta Sigma Analog to Digital Converter Design
A. Abdelaal, M. Pietzko: Continuous-time delta sigma modulators (CTDSMs) have recently become the key device for broadband wireless and wireline communication. Due to their built in anti-aliasing filter and the ability to have relaxed sampling requirements the CTDS modulators are preferred over their discrete time counterparts ... [more]
Student theses
[rp] = Bachelor theses, [mt] = Master theses
Aktuelle Arbeiten
Abgeschlossene Arbeiten
- Sherif Elsayed
Calibration of High-Speed Time-Interleaved ADCs [mt] - Mohamed Mahmoud
Investigation of Time-Interleaving in Noise-Shaped SAR ADCs [mt] - Julian Spiess
Power Efficient Delta-Sigma Modulator with Bitwise ELD Compensation [mt]
Publications
2024
9.
Pietzko,
M.;
Ungethüm,
J.;
Abdelaal,
A.;
Kauffman,
J. G.;
Ortmanns,
M.
A 600MS/s 10-bit SAR ADC with unit via-based delta-length C-DAC in 22nm FDSOI
Accepted at IEEE International Symposium on Circuits and Systems (ISCAS), Singapur
Mai 2024
A 600MS/s 10-bit SAR ADC with unit via-based delta-length C-DAC in 22nm FDSOI
Accepted at IEEE International Symposium on Circuits and Systems (ISCAS), Singapur
Mai 2024
2023
8.
Ungethüm,
J.;
Pietzko,
M.;
Abdelaal,
A.;
Kauffman,
J. G.;
Ortmanns,
M.
A Chopped 6-bit 1.6 GS/s SAR ADC Utilizing Slow Decision Information in 22 nm FDSOI
ESSCIRC 2023- IEEE 49th European Solid State Circuits Conference (ESSCIRC)
September 2023
A Chopped 6-bit 1.6 GS/s SAR ADC Utilizing Slow Decision Information in 22 nm FDSOI
ESSCIRC 2023- IEEE 49th European Solid State Circuits Conference (ESSCIRC)
September 2023
| DOI: | 10.1109/ESSCIRC59616.2023.10268704 |
7.
Pietzko,
M.;
Spiess,
J.;
Ungethüm,
J.;
Kauffman,
J. G.;
Li,
Q.;
Ortmanns,
M.
Bitwise ELD Compensation under Integrator Nonidealities in ΔΣ Modulators
21st IEEE Interregional NEWCAS Conference (NEWCAS), Edinburgh, United Kingdom
Juni 2023
Bitwise ELD Compensation under Integrator Nonidealities in ΔΣ Modulators
21st IEEE Interregional NEWCAS Conference (NEWCAS), Edinburgh, United Kingdom
Juni 2023
| DOI: | 10.1109/NEWCAS57931.2023.10198050 |
6.
Pietzko,
M.;
Ungethüm,
J.;
Kauffman,
J. G.;
Ortmanns,
M.
Delay Error Shaping in ΔΣ Modulators Using Time-Interleaved High Resolution Quantizers
IEEE Transactions on Circuits and Systems I: Regular Papers
Mai 2023
Delay Error Shaping in ΔΣ Modulators Using Time-Interleaved High Resolution Quantizers
IEEE Transactions on Circuits and Systems I: Regular Papers
Mai 2023
| DOI: | 10.1109/TCSI.2023.3269573 |
2022
5.
Pietzko,
M.;
Ungethüm,
J.;
Kauffman,
J. G.;
Li,
Q.;
Ortmanns,
M.
Bitwise ELD Compensation in ∆Σ Modulators
IEEE International Symposium on Circuits and Systems (ISCAS), Austin, USA
Mai 2022
Bitwise ELD Compensation in ∆Σ Modulators
IEEE International Symposium on Circuits and Systems (ISCAS), Austin, USA
Mai 2022
| DOI: | 10.1109/ISCAS48785.2022.9937305 |
4.
Ungethüm,
J.;
Pietzko,
M.;
Kauffman,
J. G.;
Li,
Q.;
Ortmanns,
M.
Maximizing the Inter-Stage Gain in CT 0-X MASH Delta-Sigma-Modulators
IEEE International Symposium on Circuits and Systems (ISCAS), Austin, TX, USA
Mai 2022
Maximizing the Inter-Stage Gain in CT 0-X MASH Delta-Sigma-Modulators
IEEE International Symposium on Circuits and Systems (ISCAS), Austin, TX, USA
Mai 2022
| DOI: | 10.1109/ISCAS48785.2022.9937739 |
2021
3.
Ezekwe,
C.;
Ganta,
S.;
Xing,
X.;
Grad,
A.;
Mayer,
T.;
Visconti,
A.;
Diazzi,
F.;
Chen,
M.;
Morton,
D.;
Valli,
L.;
Wolf,
R.;
Eghtesadi,
A.;
Wolfer,
T.;
Pietzko,
M.;
Grathwohl,
A.;
Northemann,
T.;
Schoenleber,
R.;
Khalilyulin,
R.;
Mukhopadhyay,
I.;
Negut,
A.;
Kosov,
A.;
Serafin,
A.;
Hayek,
J.;
Sun,
L.
A direct-digitization open-loop gyroscope frontend with +/-8000°/s full-scale range and noise floor of 0.0047°/s/√Hz
Symposium on VLSI Circuits, 2021, pp. 1-2
Juni 2021
A direct-digitization open-loop gyroscope frontend with +/-8000°/s full-scale range and noise floor of 0.0047°/s/√Hz
Symposium on VLSI Circuits, 2021, pp. 1-2
Juni 2021
| DOI: | 10.23919/VLSICircuits52068.2021.9492404 |
2.
Abdelaal,
A.;
Pietzko,
M.;
Mokhtar,
M. A.;
Kauffman,
J. G.;
Ortmanns,
M.
FIR filter with Symmetric Non-Equal Coefficients for CT Delta-Sigma Modulators
IEEE International Symposium on Circuits and Systems (ISCAS), Daegu, Korea (Online)
Mai 2021
FIR filter with Symmetric Non-Equal Coefficients for CT Delta-Sigma Modulators
IEEE International Symposium on Circuits and Systems (ISCAS), Daegu, Korea (Online)
Mai 2021
1.
Pietzko,
M.;
Wagner,
J.;
Abdelaal,
A.;
Kauffman,
J. G.;
Ortmanns,
M.
Influence of Excess Loop Delay on the STF of Continuous-Time Delta-Sigma Modulators
IEEE International Symposium on Circuits and Systems (ISCAS), Daegu, Korea (Online)
Mai 2021
Influence of Excess Loop Delay on the STF of Continuous-Time Delta-Sigma Modulators
IEEE International Symposium on Circuits and Systems (ISCAS), Daegu, Korea (Online)
Mai 2021
Wissenschaftl. Mitarbeiter
