Mixed Signal CMOS Chip Design
This lecture goes along with the analog and digital CMOS circuit design lectures
offered by the institute of microelectronics. In contrast to these more
theoretical lectures on circuit design techniques, this lecture is focused on the
implementation issues of application specific integrated circuits (ASICs).
- new dates will be announced
- analog simulation
- digital simulation
- mixed-signal and co-simulation
- design for reliability
- design for testability
- CMOS layout, floorplanning, standart-cells
- layout parasitic extraction and verification
- packaging and board design
After successful pass of this course, students understand the working principles of analog and digital circuit simulation techniques. They are able to set up a node admittance matrix from a given circuit and know the working principles and applications of the three main analog simulation types: DC, AC, and transient. They understand linearization of device models and Newton-Raphson integration for solution of differential equations, update and residue criteria, and equilibrium points. Furthermore, they understand process variation and device mismatch and their influence on CMOS circuits and are able to use worst case corner modeling and statistical evaluation methods like Monte Carlo analysis for yield optimization and design centering. They can elaborate the difference between cycle-based and event-driven digital simulation techniques, including half-step simulation and time-wheel scheduling. They are able to use setupand hold-time constraints as well as contamination- and propagation-delays for calculation of slack times in a static timing analysis and can explain the effect of clock skew and jitter on synchronous circuits. They can elaborate how table-based models and circuit-partitioning is able to significantly speed up simulations and enables mixed-signal verification. They can estimate the tradeoff between manual modeling, compiled-model interface, and coupled co-simulation for mixed-mode analyses. They understand synthesis of combinational and synchronous behavioral hardware description into generic gates. Furthermore, they are able to use the stuck-at fault-model and the D-algorithm in order to analyze testability and include boundary-scan Flip-Flops for improved testability. They know principles of placement and routing of standard-cells including mincut algorithm, maze- and channel-routing, and layout compaction, as well as design-rule-check and layout-versus-schematic-check. They are able to build a clock-distribution network and make use of timing aware placement, as well as build a power-grid and apply I/O-cells in order to improve the reliability of digital circuits. Finally, they know various bonding-techniques and printed-circuit-board design practices in order to connect the final ASIC to other chips and measurement equipment.
There is a strong emphasis on the computer aided design (CAD) support and
algorithms, which are integral part of todays chip implementation. The exercises
will be used to give hands-on experience with industry-standart CAD design tools.
The online part of the study programme takes place in self studies and in form of group work. For the self study part video lectures with detailed information about the contents and an elaborated script is offered. The script is developed especially for extra-occupational learners in regard to the didactic concept of Ulm University. It contains learning stopps, multiple and single choice tests, quizzes, exercises, etc.
Your mentor will offer online seminars in periodic intervals. These seminars will help you handling the exercises and working on the learning matters. An online forum for exchange with the other students will also be available.
Requirement is a first graduate degree.
Contentual: Basics of CMOS technology, analog circuit design, digital circuit design
- Ein Desktop-Rechner oder ein Notebook mit einer aktuellen, d.h. vom jeweiligen Hersteller unterstützten Version von Microsoft Windows, Apple macOS oder Linux
- Ein Headset
- Die aktuelle Version von Mozilla Firefox, Google Chrome, Apple Safari oder Microsoft Edge
- Internet-Zugang (z.B. über xDSL, Cable, LTE, 5G) mit mindestens 3 Mbit/s in Downstream- und 384 kbit/s in Upstream-Richtung ("DSL 3000").
Bitte zögern Sie nicht, uns bei Fragen zu den technischen Anforderungen zu kontaktieren.
Regular participation in online seminars will help you solving exercises, which have to be loaded up to the learning management system after request of the mentor. Passing the exercises successfully is recommended for participation in the final examination at Ulm University.
After finishing your exame successfully you will get a certificate and a supplement, which will list the contents of the module and the competencies you have acquired. In the supplement the responsible person for the module confirms you the equivalent of 4 credit points (ECTS).
Participation fee for certificate course: 780 Euro
Fee after matriculation: 660 Euro
Dr.-Ing. Joachim Becker
Group Leader in the Institute of Microelectronics